[PATCH] powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors

[Nicholas Piggin]

Excerpts from Michael Ellerman's message of April 7, 2021 9:33 pm:
> Nicholas Piggin <npiggin at gmail.com> writes:
>> Starting with ISA v3.1, LPCR[AIL] no longer controls the interrupt
>> mode for HV=1 interrupts. Instead, a new LPCR[HAIL] bit is defined
>> which behaves like AIL=3 for HV interrupts when set.
>>
>> Set HAIL on bare metal to give us mmu-on interrupts and improve
>> performance.
>>
>> This also fixes an scv bug: we don't implement scv real mode (AIL=0)
>> vectors because they are at an inconvenient location, so we just
>> disable scv support when AIL can not be set. However powernv assumes
>> that LPCR[AIL] will enable AIL mode so it enables scv support despite
>> HV interrupts being AIL=0, which causes scv interrupts to go off into
>> the weeds.
> 
> Should we tag this as fixing the initial P10 support, or the scv
> support? Or neither?

Good question. It does fix a nasty crash with scv so at least it should
be tagged I guess.

I don't know of anything else that assumes AIL on bare metal, so I don't 
know of a crashy bug it fixes with initial P10 support. But it is a bit 
odd for a HV OS running a v3.1 processor to set the old LPCR AIL bits, 
so it is some kind of bug fix (performance at least).

Could go either way I guess.

Thanks,
Nick


> 
> cheers
> 
>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
>> index 1be20bc8dce2..9086a2644c89 100644
>> --- a/arch/powerpc/include/asm/reg.h
>> +++ b/arch/powerpc/include/asm/reg.h
>> @@ -441,6 +441,7 @@
>>  #define   LPCR_VRMA_LP1		ASM_CONST(0x0000800000000000)
>>  #define   LPCR_RMLS		0x1C000000	/* Implementation dependent RMO limit sel */
>>  #define   LPCR_RMLS_SH		26
>> +#define   LPCR_HAIL		ASM_CONST(0x0000000004000000)   /* HV AIL (ISAv3.1) */
>>  #define   LPCR_ILE		ASM_CONST(0x0000000002000000)   /* !HV irqs set MSR:LE */
>>  #define   LPCR_AIL		ASM_CONST(0x0000000001800000)	/* Alternate interrupt location */
>>  #define   LPCR_AIL_0		ASM_CONST(0x0000000000000000)	/* MMU off exception offset 0x0 */
>> diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
>> index 04a31586f760..671192afcdfd 100644
>> --- a/arch/powerpc/kernel/setup_64.c
>> +++ b/arch/powerpc/kernel/setup_64.c
>> @@ -233,10 +233,23 @@ static void cpu_ready_for_interrupts(void)
>>  	 * If we are not in hypervisor mode the job is done once for
>>  	 * the whole partition in configure_exceptions().
>>  	 */
>> -	if (cpu_has_feature(CPU_FTR_HVMODE) &&
>> -	    cpu_has_feature(CPU_FTR_ARCH_207S)) {
>> +	if (cpu_has_feature(CPU_FTR_HVMODE)) {
>>  		unsigned long lpcr = mfspr(SPRN_LPCR);
>> -		mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
>> +		unsigned long new_lpcr = lpcr;
>> +
>> +		if (cpu_has_feature(CPU_FTR_ARCH_31)) {
>> +			/* P10 DD1 does not have HAIL */
>> +			if (pvr_version_is(PVR_POWER10) &&
>> +					(mfspr(SPRN_PVR) & 0xf00) == 0x100)
>> +				new_lpcr |= LPCR_AIL_3;
>> +			else
>> +				new_lpcr |= LPCR_HAIL;
>> +		} else if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
>> +			new_lpcr |= LPCR_AIL_3;
>> +		}
>> +
>> +		if (new_lpcr != lpcr)
>> +			mtspr(SPRN_LPCR, new_lpcr);
>>  	}
>>  
>>  	/*
>> -- 
>> 2.23.0
>