[PATCH v5 1/5] powerpc/sstep: Emulate prefixed instructions only when CPU_FTR_ARCH_31 is set

[Ravi Bangoria]

Hi Daniel,

On 10/12/20 7:14 PM, Daniel Axtens wrote:
> Hi,
> 
> To review this, I looked through the supported instructions to see if
> there were any that I thought might have been missed.
> 
> I didn't find any other v3.1 ones, although I don't have a v3.1 ISA to
> hand so I was basically looking for instructions I didn't recognise.
> 
> I did, however, find a number of instructions that are new in ISA 3.0
> that aren't guarded:
> 
>   - addpcis
>   - lxvl/stxvl
>   - lxvll/stxvll
>   - lxvwsx
>   - stxvx
>   - lxsipzx
>   - lxvh8x
>   - lxsihzx
>   - lxvb16x/stxvb16x
>   - stxsibx
>   - stxsihx
>   - lxvb16x
>   - lxsd/stxsd
>   - lxssp/stxssp
>   - lxv/stxv
>   
> Also, I don't know how bothered we are about P7, but if I'm reading the
> ISA correctly, lqarx/stqcx. are not supported before ISA 2.07. Likewise
> a number of the vector instructions like lxsiwzx and lxsiwax (and the
> companion stores).
> 
> I realise it's not really the point of this particular patch, so I don't
> think this should block acceptance. What I would like to know - and
> maybe this is something where we need mpe to weigh in - is whether we
> need consistent guards for 2.07 and 3.0. We have some 3.0 guards already
> but clearly not everywhere.

Yes, those needs to be handled properly. Otherwise they can be harmful
when emulated on a non-supporting platform. Will work on it when I get
some time. Thanks for reporting it.

> 
> With all that said - the patch does what it says it does, and looks good
> to me:
> 
> Reviewed-by: Daniel Axtens <dja at axtens.net>

Thanks!
Ravi