bpf jit PPC64 (BE) test_verifier PTR_TO_STACK store/load failure
Naveen N. Rao
naveen.n.rao at linux.ibm.com
Sat Mar 16 00:16:45 AEDT 2019
Segher Boessenkool wrote:
> On Wed, Mar 13, 2019 at 12:54:16PM +0200, Yauheni Kaliuta wrote:
>> This is because of the handling of the +2 offset.
> The low two bits of instructions with primary opcodes 58 and 62 are part
> of the opcode, not the offset. These instructions can not have offsets
> with the low two bits non-zero.
>> For stores it is:
>> #define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \
>> ___PPC_RA(base) | ((i) & 0xfffc))
>> and for loads
>> #define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \
>> ___PPC_RA(base) | IMM_L(i))
>> #define IMM_L(i) ((uintptr_t)(i) & 0xffff)
>> So, in the load case the offset +2 (immediate value) is not
>> masked and turns the instruction to lwa instead of ld.
>> Would it be correct to & 0xfffc the immediate value as well?
> That is only part of it. The other thing is you have to make sure those
> low bits are zero *already* (and then you do not need the mask anymore).
> For example, if the low two bits are not zero load the offset into a
> register instead (and then do ldx or lwax).
Thanks for pointing that out, Segher. That is a detail that is easily
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