[PATCH v2 8/8] habanalabs: enable 64-bit DMA mask in POWER9
Benjamin Herrenschmidt
benh at kernel.crashing.org
Wed Jun 12 08:53:07 AEST 2019
On Tue, 2019-06-11 at 20:22 +0300, Oded Gabbay wrote:
>
> > So, to summarize:
> > If I call pci_set_dma_mask with 48, then it fails on POWER9. However,
> > in runtime, I don't know if its POWER9 or not, so upon failure I will
> > call it again with 32, which makes our device pretty much unusable.
> > If I call pci_set_dma_mask with 64, and do the dedicated configuration
> > in Goya's PCIe controller, then it won't work on x86-64, because bit
> > 59 will be set and the host won't like it (I checked it). In addition,
> > I might get addresses above 50 bits, which my device can't generate.
> >
> > I hope this makes things more clear. Now, please explain to me how I
> > can call pci_set_dma_mask without any regard to whether I run on
> > x86-64 or POWER9, considering what I wrote above ?
> >
> > Thanks,
> > Oded
>
> Adding ppc mailing list.
You can't. Your device is broken. Devices that don't support DMAing to
the full 64-bit deserve to be added to the trash pile.
As a result, getting it to work will require hacks. Some GPUs have
similar issues and require similar hacks, it's unfortunate.
Added a couple of guys on CC who might be able to help get those hacks
right.
It's still very fishy .. the idea is to detect the case where setting a
64-bit mask will give your system memory mapped at a fixed high address
(1 << 59 in our case) and program that in your chip in the "Fixed high
bits" register that you seem to have (also make sure it doesn't affect
MSIs or it will break them).
This will only work as long as all of the system memory can be
addressed at an offset from that fixed address that itself fits your
device addressing capabilities (50 bits in this case). It may or may
not be the case but there's no way to check since the DMA mask logic
won't really apply.
You might want to consider fixing your HW in the next iteration... This
is going to bite you when x86 increases the max physical memory for
example, or on other architectures.
Cheers,
Ben.
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