[PATCH] powerpc: workaround clang codegen bug in dcbz
segher at kernel.crashing.org
Tue Jul 30 07:52:00 AEST 2019
On Mon, Jul 29, 2019 at 01:32:46PM -0700, Nathan Chancellor wrote:
> For the record:
> This seems consistent with what Michael found so I don't think a revert
> is entirely unreasonable.
This matters in non-trivial loops, for example. But all current cases
where such non-trivial loops are done with cache block instructions are
actually written in real assembler already, using two registers.
Because performance matters. Not that I recommend writing code as
critical as memset in C with inline asm :-)
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