[PATCH v4 5/8] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache

[Claudio Carvalho]

On 7/1/19 2:54 AM, Alexey Kardashevskiy wrote:
>
> On 29/06/2019 06:08, Claudio Carvalho wrote:
>> From: Ram Pai <linuxram at us.ibm.com>
>>
>> Ultravisor is responsible for flushing the tlb cache, since it manages
>> the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
>> available.
>>
>> Signed-off-by: Ram Pai <linuxram at us.ibm.com>
>> Signed-off-by: Claudio Carvalho <cclaudio at linux.ibm.com>
>> ---
>>  arch/powerpc/mm/book3s64/pgtable.c | 33 +++++++++++++++++-------------
>>  1 file changed, 19 insertions(+), 14 deletions(-)
>>
>> diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3s64/pgtable.c
>> index 224c5c7c2e3d..bc8eb2bf9810 100644
>> --- a/arch/powerpc/mm/book3s64/pgtable.c
>> +++ b/arch/powerpc/mm/book3s64/pgtable.c
>> @@ -224,6 +224,23 @@ void __init mmu_partition_table_init(void)
>>  	powernv_set_nmmu_ptcr(ptcr);
>>  }
>>  
>> +static void flush_partition(unsigned int lpid, unsigned long dw0)
>> +{
>> +	if (dw0 & PATB_HR) {
>> +		asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
>> +			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
>> +		asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
>> +			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
>> +		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
>> +	} else {
>> +		asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
>> +			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
>> +		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
>> +	}
>> +	/* do we need fixup here ?*/
>> +	asm volatile("eieio; tlbsync; ptesync" : : : "memory");
>> +}
>> +
>>  static void __mmu_partition_table_set_entry(unsigned int lpid,
>>  					    unsigned long dw0,
>>  					    unsigned long dw1)
>> @@ -238,20 +255,8 @@ static void __mmu_partition_table_set_entry(unsigned int lpid,
>>  	 * The type of flush (hash or radix) depends on what the previous
>>  	 * use of this partition ID was, not the new use.
>>  	 */
>> -	asm volatile("ptesync" : : : "memory");
>> -	if (old & PATB_HR) {
>> -		asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
>> -			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
>> -		asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
>> -			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
>> -		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
>> -	} else {
>> -		asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
>> -			     "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
>> -		trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
>> -	}
>> -	/* do we need fixup here ?*/
>> -	asm volatile("eieio; tlbsync; ptesync" : : : "memory");
>> +	if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR))
>
> __mmu_partition_table_set_entry() checks for UV and
> mmu_partition_table_set_entry() (the caller) checks for UV and the whole
> point of having separate flush_partition() and
> __mmu_partition_table_set_entry() is not really clear.
>
>
> 4/8 and 5/8 make more sense as one patch imho.


Makes sense. I merged them in the next version. Thanks.

Claudio


>
>
>> +		flush_partition(lpid, old);
>>  }
>>  
>>  void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
>>