[PATCH 0/3] powerpc: sstep: Emulation test infrastructure

[Sandipan Das]

This aims to extend the current test infrastructure for in-kernel
instruction emulation by adding support for validating basic integer
operations and will verify the GPRs, LR, XER and CR.

There can be multiple test cases for each instruction. Each test case
has to be provided with the initial register state (in the form of a
pt_regs) and the 32-bit instruction to test.

Apart from verifying the end result, problems with the behaviour of
certain instructions for things like setting certain bits in CR or
XER (which can also be processor dependent) can be identified.

For example, the newly introduced CA32 bit in XER, exclusive to P9
CPUs as of now, was not being set when expected for some of the
arithmetic and shift instructions. With this infrastructure, it will
be easier to identify such problems and rectify them. The test cases
for the addc[.] instruction demonstrate this for different scenarios
where the CA and CA32 bits of XER should be set.

Changelog:
  RFC -> v1:
    - Integrate with current test infrastructure that already tests
      some load and store instructions.
    - Remove first two patches that introduce new instructions fields
      in favour of extending the macros in the current infrastructure.
    - Add a message to indicate that the tests are being run based on
      suggestions from Daniel.

Sandipan Das (3):
  powerpc: sstep: Add tests for compute type instructions
  powerpc: sstep: Add tests for add[.] instruction
  powerpc: sstep: Add tests for addc[.] instruction

 arch/powerpc/include/asm/ppc-opcode.h         |   1 +
 arch/powerpc/lib/Makefile                     |   3 +-
 arch/powerpc/lib/test_emulate_step.c          | 535 +++++++++++++++++-
 .../lib/test_emulate_step_exec_instr.S        | 150 +++++
 4 files changed, 684 insertions(+), 5 deletions(-)
 create mode 100644 arch/powerpc/lib/test_emulate_step_exec_instr.S

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2.19.2