[PATCH v8 0/3] powerpc: Detection and scheduler optimization for POWER9 bigcore

[Gautham R Shenoy]

Hello Dave,

On Tue, Sep 25, 2018 at 03:16:30PM -0700, Dave Hansen wrote:
> On 09/22/2018 04:03 AM, Gautham R Shenoy wrote:
> > Without this patchset, the SMT domain would be defined as the group of
> > threads that share L2 cache.
> 
> Could you try to make a more clear, concise statement about the current
> state of the art vs. what you want it to be?  Right now, the sched
> domains do something like this in terms of ordering:
> 
> 1. SMT siblings
> 2. Caches
> 3. NUMA

Yes. you are right. The state of art on POWER9 machines having SMT8
cores is as you described above with

1. SMT siblings sharing L2-cache, called the SMT domain
2. Cores on the same die, called the DIE domain
3. NUMA

> 
> It sounds like you don't want SMT siblings to be the things that we use,
> right?  Because some siblings share caches and some do not.  Right?  You
> want something like this:
> 
> 1. SMT siblings (sharing L1)
> 2. SMT siblings (sharing L2)
> 3. Other caches
> 4. NUMA
>

Yes, with the patchset the sched-domain hierarchy on POWER9 machines
having SMT8 will be:

1. SMT siblings sharing L1 cache, called the SMT domain
2. SMT siblings sharing L2 cache, called the CACHE domain (introduced in
   commit 96d91431d691 "powerpc/smp: Add Power9 scheduler topology")
3. Cores on the same die, called the DIE domain.
4. NUMA

--
Thanks and Regards
gautham.