[PATCH v2 5/6] net/wan/fsl_ucc_hdlc: GUMR for non tsa mode

christophe leroy christophe.leroy at c-s.fr
Sat Sep 1 18:08:23 AEST 2018



Le 29/08/2018 à 15:13, David Gounaris a écrit :
> The following bits in the GUMR is changed for non
> tsa mode: CDS, CTSP and CTSS are set to zero.
> 
> When set, there is no tx interrupts from the controller.
> 
> Signed-off-by: David Gounaris <david.gounaris at infinera.com>
> ---
>   drivers/net/wan/fsl_ucc_hdlc.c | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
> index be5b0096af3b..248f1f5bcd04 100644
> --- a/drivers/net/wan/fsl_ucc_hdlc.c
> +++ b/drivers/net/wan/fsl_ucc_hdlc.c
> @@ -97,6 +97,13 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
>   	if (priv->tsa) {
>   		uf_info->tsa = 1;
>   		uf_info->ctsp = 1;
> +		uf_info->cds = 1;
> +		uf_info->ctss = 1;
> +	}
> +	else {

ERROR:ELSE_AFTER_BRACE: else should follow close brace '}'
#27: FILE: drivers/net/wan/fsl_ucc_hdlc.c:103:
+	}
+	else {

CHECK:BRACES: Unbalanced braces around else statement
#27: FILE: drivers/net/wan/fsl_ucc_hdlc.c:103:
+	else {

Should be:

} else {

> +		uf_info->cds = 0;
> +		uf_info->ctsp = 0;
> +		uf_info->ctss = 0;
>   	}
>   
>   	/* This sets HPM register in CMXUCR register which configures a
> 

---
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