[PATCH 2/2] powerpc/mm/radix: Change pte relax sequence to handle nest MMU hang

[Nicholas Piggin]

On Fri, 25 May 2018 21:19:17 +0530
"Aneesh Kumar K.V" <aneesh.kumar at linux.ibm.com> wrote:

> When relaxing access (read -> read_write update), pte need to be marked invalid
> to handle a nest MMU bug. We also need to do a tlb flush after the pte is
> marked invalid before updating the pte with new access bits.
> 
> We also move tlb flush to platform specific __ptep_set_access_flags. This will
> help us to gerid of unnecessary tlb flush on BOOK3S 64 later. We don't do that
> in this patch. This also helps in avoiding multiple tlbies with coprocessor
> attached.
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar at linux.ibm.com>

I think these look good to me, but same comment: can you split the API
change from the NMMU fix? The fix is just a couple of lines, and the
rest of the API change should leave generated code almost unchanged, so
it would be easier to review if these are split.

Thanks,
Nick