[PATCH kernel] powerpc/powernv/ioda2: Reduce upper limit for DMA window size

[Michael Ellerman]

Alexey Kardashevskiy <aik at ozlabs.ru> writes:

> We use PHB in mode1 which uses bit 59 to select a correct DMA window.
> However there is mode2 which uses bits 59:55 and allows up to 32 DMA
> windows per a PE.

Do we ever use mode2?

> Even though documentation does not clearly specify that, it seems that
> the actual hardware does not support bits 59:55 even in mode1, in other
> words we can create a window as big as 1<<58 but DMA simply won't work.

Can we get anything more solid than "seems that" ?

Is this documented somewhere to not work or you just found this by
testing?

> This reduces the upper limit from 59 to 55 bits to let the userspace know
> about the hardware limits.
>
> Fixes: 7aafac11e3 "powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested"

Stable?

cheers

> Signed-off-by: Alexey Kardashevskiy <aik at ozlabs.ru>
> ---
>  arch/powerpc/platforms/powernv/pci-ioda.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
> index 92ca662..50e21d7 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -2839,7 +2839,7 @@ static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
>  	level_shift = entries_shift + 3;
>  	level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
>  
> -	if ((level_shift - 3) * levels + page_shift >= 60)
> +	if ((level_shift - 3) * levels + page_shift >= 55)
>  		return -EINVAL;
>  
>  	/* Allocate TCE table */
> -- 
> 2.11.0