[PATCH V3] cxl: Fix timebase synchronization status on P9

[christophe lombard]

Le 19/02/2018 à 07:10, Vaibhav Jain a écrit :
> 
> Hi Christophe,
> 
> Mostly ok with this patch. Some very minor review comments:
> 
> Christophe Lombard <clombard at linux.vnet.ibm.com> writes:
>> --- a/drivers/misc/cxl/sysfs.c
>> +++ b/drivers/misc/cxl/sysfs.c
>> @@ -62,6 +62,16 @@ static ssize_t psl_timebase_synced_show(struct device *device,
>>   					char *buf)
>>   {
>>   	struct cxl *adapter = to_cxl_adapter(device);
>> +	u64 psl_tb;
>> +	int delta;
>> +
>> +	psl_tb = adapter->native->sl_ops->timebase_read(adapter);
>> +	delta = mftb() - psl_tb;
>> +	if (delta < 0)
>> +		delta = -delta;
> Can just use abs().

okay, I can.

>> +
>> +	/* CORE TB and PSL TB difference <= 16usecs ? */
>> +	adapter->psl_timebase_synced = (tb_to_ns(delta) < 16000) ? true : false;
> Can be re-written as
> 'adapter->psl_timebase_synced = (tb_to_ns(abs(delta)) < 16000);'

I prefer to keep the original version for easier reading.

> 
>>
>>   	return scnprintf(buf, PAGE_SIZE, "%i\n",
>>   	adapter->psl_timebase_synced);
> Might be a good idea to debug print/print_once the delta.

sounds good.

>