[PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9

[Frederic Barrat]

Le 09/02/2018 à 05:09, Vaibhav Jain a écrit :
> We enable the NORST bit by default for debug afu images to prevent
> reset of AFU trace-data on a PCI link drop. For production AFU images
> this bit is always ignored and PSL gets reconfigured anyways thereby
> resetting the trace data. So setting this bit for non-debug images
> doesn't have any impact.
> 
> Signed-off-by: Vaibhav Jain <vaibhav at linux.vnet.ibm.com>
> ---

Acked-by: Frederic Barrat <fbarrat at linux.vnet.ibm.com>

btw, we should start removing dd1 code, it's not like anybody is going 
to try that now.

   Fred

>   drivers/misc/cxl/pci.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index 758842f65a1b..c983f23cc2ed 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -503,8 +503,12 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
>   	if (cxl_is_power9_dd1()) {
>   		/* Disabling deadlock counter CAR */
>   		cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
> -	} else
> -		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
> +		/* Enable NORST */
> +		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
> +	} else {
> +		/* Enable NORST and DD2 features */
> +		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
> +	}
> 
>   	return 0;
>   }
>