[PATCH] powerpc/4xx/ocm: fix compiler error

[Gabriel Paubert]

On Sat, Dec 22, 2018 at 05:04:51PM -0600, Segher Boessenkool wrote:
> On Sat, Dec 22, 2018 at 08:37:28PM +0100, christophe leroy wrote:
> > Le 22/12/2018 à 18:16, Segher Boessenkool a écrit :
> > >On Sat, Dec 22, 2018 at 02:08:02PM +0100, christophe leroy wrote:
> > >>
> > >>Usually, Guarded implies no exec (at least on 6xx and 8xx).
> > >
> > >Huh?  What do you mean here?
> > 
> > From the 885 Reference Manual:
> > 
> > Address translation: the EA is translated by using the MMU’s TLB 
> > mechanism. Instructions are not fetched from no-execute or guarded 
> > memory and data accesses are not executed speculatively to or from the 
> > guarded memory.
> > 
> > 6.1.3.4 Instruction TLB Error Exception (0x01300)
> > This type of exception occurs as a result of one of the following 
> > conditions if MSR[IR] = 1:
> > - The EA cannot be translated.
> > - The fetch access violates memory protection
> > - The fetch access is to guarded memory
> > 
> > 
> > From e300core reference manual:
> > 
> > Translation Exception Conditions:
> > Exception condition: Instruction fetch from guarded memory
> > with MSR[IR] = 1 ==> ISI interrupt SRR1[3] = 1
> 
> Right, but you said 6xx as well, i.e. pure PowerPC.
> 
> If for example IR=0 you cannot have N=1, but you do have G=1.  There is
> no case where G=1 implies N=1 afaik, or where fetch is prohibited some
> other way (causes an ISI, say).

>From the 750fx user's manual, similar wording can be found for other
processors (except 601), including the ones that use software TLB load
like 603/603e (the test for guarded memory is in the sample code for
the tlb miss handler):

"
An ISI exception occurs when no higher priority exception exists and an
attempt to fetch the next instruction fails. This exception is implemented 
as it is defined by the PowerPC architecture (OEA), and is taken for the
following conditions:
•   The effective address cannot be translated.
•   The fetch access is to a no-execute segment (SR[N] = 1).
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
•   The fetch access is to guarded storage and MSR[IR] = 1.
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
•   The fetch access is to a segment for which SR[T] is set.
•   The fetch access violates memory protection.
When an ISI exception is taken, instruction fetching resumes at offset
0x00400 from the physical base indicated by MSR[IP].
"

	Gabriel