[PATCH 5/5] powerpc/smp: Add Power9 scheduler topology

[Balbir Singh]

On 02/03/17 11:49, Oliver O'Halloran wrote:
> In previous generations of Power processors each core had a private L2
> cache. The Power9 processor has a slightly different architecture where
> the L2 cache is shared among pairs of cores rather than being completely
> private.
> 
> Making the scheduler aware of this cache sharing allows the scheduler to
> make more intelligent migration decisions. When one core in the pair is
> overloaded tasks can be migrated to its paired core to improve throughput
> without cache-refilling penality typically associated with task
> migration.

Could you please describe the changes to sched_domains w.r.t before and
after for P9.

I think most of the changes make sense, but some data to back them up
including any results you have to show that these patches help would be
nice

Balbir Singh.