[PATCH v2] powerpc: A new cache geometry aux vectors

[Michael Ellerman]

Paul Clarke <pc at us.ibm.com> writes:

> On 02/02/2017 12:22 AM, Benjamin Herrenschmidt wrote:
>> This adds AUX vectors for the L1I,D, L2 and L3 cache levels
>> providing for each cache level the size of the cache in bytes
>> and the geometry (line size and number of ways).
>>
>> We chose to not use the existing alpha/sh definition which
>> packs all the information in a single entry per cache level as
>> it is too restricted to represent some of the geometries used
>> on POWER.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
>> ---
>>
>> v2. Remove some leftovers and fix 32-bit build
>>
>> Paul, can you test & ack this please ? It replaces the last patch of
>> my previous series (the rest is identical).
>
> Sorry for the delay on this, I totally missed this e-mail until this week.
>
> I tested this with the Power Functional Simulator (a.k.a. Mambo), with
> a fairly recent 4.9 kernel from the powerpc git tree.

You mean 4.9 plus this patch?

> Using Mambo-P8, I see what I expect for cache line size, but associativity is 0:
> AT_L1I_CACHESIZE: 32768 (0x8000)
> AT_L1I_CACHEGEOMETRY: associativity 0; line size 128
> AT_L1D_CACHESIZE: 32768 (0x8000)
> AT_L1D_CACHEGEOMETRY: associativity 0; line size 128
> AT_L2_CACHESIZE: 524288 (0x80000)
> AT_L2_CACHEGEOMETRY: associativity 0; line size 128
> AT_L3_CACHESIZE: 8388608 (0x800000)
> AT_L3_CACHEGEOMETRY: associativity 0; line size 128
>
> ...shouldn't associativity be 8 for all levels?

Yes.

I fixed it in v3: http://patchwork.ozlabs.org/patch/723576/

Which is now merged in Linus tree, so please test that.

Can you try the test program I wrote (which may also have bugs):

  http://patchwork.ozlabs.org/patch/724418/

cheers