[PATCH] powerpc/ipic: Support edge on IRQ0
Jürgen Schindele
schindele at nentec.de
Mon Jun 26 22:55:45 AEST 2017
Index 48 equals IRQ0 in developpers manual
Am 26.06.2017 um 14:46 schrieb Michael Ellerman:
> Scott Wood <oss at buserror.net> writes:
>
>> External IRQ0 has the same capabilities as the other IRQ1-7 and is
>> handled by the same register IPIC_SEPNR. When this register is not
>> specified for "ack" in "ipic_info", you cannot configure this IRQ as
>> IRQ_TYPE_EDGE_FALLING. This oversight was probably due to the
>> non-contiguous hwirq numbering of IRQ0 in the IPIC.
> I don't know this code at all, but nothing in the diff says "IRQ0" to
> me?
>
> cheers
>
>> diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
>> index f267ee0afc08..16f1edd78c40 100644
>> --- a/arch/powerpc/sysdev/ipic.c
>> +++ b/arch/powerpc/sysdev/ipic.c
>> @@ -315,6 +315,7 @@ static struct ipic_info ipic_info[] = {
>> .prio_mask = 7,
>> },
>> [48] = {
>> + .ack = IPIC_SEPNR,
>> .mask = IPIC_SEMSR,
>> .prio = IPIC_SMPRR_A,
>> .force = IPIC_SEFCR,
>> --
>> 2.11.0
--
i. A.
Jürgen Schindele
Softwareentwicklung
PSI Nentec GmbH
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schindele at nentec.de
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