[PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly

Vinod Koul vinod.koul at intel.com
Thu Jun 22 23:01:57 AEST 2017


On Mon, Jun 19, 2017 at 04:40:04PM +0200, Thomas Breitung wrote:
> The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared
> before a new value can be or-ed in.

Applied, thanks

-- 
~Vinod


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