[PATCH] powerpc/perf: Fix POWER9 branch event

[Madhavan Srinivasan]

On Monday 19 June 2017 09:25 AM, Anton Blanchard wrote:
> From: Anton Blanchard <anton at samba.org>
>
> The POWER9 branch event is wrong, and we always get a count of zero:
>
> ...
>                   0      branches
>                3844      branch-misses             #    0.00% of all branches
>
> Replace it with the correct event.
Anton,

How about this patch,  this will force DD1 to use 0x10012 for
branch and later to use 0x4d05e ?

diff --git a/arch/powerpc/perf/power9-events-list.h 
b/arch/powerpc/perf/power9-events-list.h
index 71a6bfee5c02..13bd159db300 100644
--- a/arch/powerpc/perf/power9-events-list.h
+++ b/arch/powerpc/perf/power9-events-list.h
@@ -16,7 +16,7 @@ EVENT(PM_CYC,                    0x0001e)
  EVENT(PM_ICT_NOSLOT_CYC,            0x100f8)
  EVENT(PM_CMPLU_STALL,                0x1e054)
  EVENT(PM_INST_CMPL,                0x00002)
-EVENT(PM_BRU_CMPL,                0x10012)
+EVENT(PM_BR_CMPL,                0x4d05e)
  EVENT(PM_BR_MPRED_CMPL,                0x400f6)

  /* All L1 D cache load references counted at finish, gated by reject */
@@ -56,3 +56,4 @@ EVENT(PM_RUN_CYC,                0x600f4)
  /* Instruction Dispatched */
  EVENT(PM_INST_DISP,                0x200f2)
  EVENT(PM_INST_DISP_ALT,                0x300f2)
+EVENT(PM_BR_CMPL_ALT,                0x10012)
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index bb28e1a41257..485dacf30152 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -123,7 +123,7 @@ GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
  GENERIC_EVENT_ATTR(stalled-cycles-frontend,    PM_ICT_NOSLOT_CYC);
  GENERIC_EVENT_ATTR(stalled-cycles-backend,    PM_CMPLU_STALL);
  GENERIC_EVENT_ATTR(instructions,        PM_INST_CMPL);
-GENERIC_EVENT_ATTR(branch-instructions,        PM_BRU_CMPL);
+GENERIC_EVENT_ATTR(branch-instructions,        PM_BR_CMPL);
  GENERIC_EVENT_ATTR(branch-misses,        PM_BR_MPRED_CMPL);
  GENERIC_EVENT_ATTR(cache-references,        PM_LD_REF_L1);
  GENERIC_EVENT_ATTR(cache-misses,        PM_LD_MISS_L1_FIN);
@@ -141,7 +141,7 @@ CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
  CACHE_EVENT_ATTR(LLC-store-misses,        PM_L2_ST_MISS);
  CACHE_EVENT_ATTR(LLC-stores,            PM_L2_ST);
  CACHE_EVENT_ATTR(branch-load-misses,        PM_BR_MPRED_CMPL);
-CACHE_EVENT_ATTR(branch-loads,            PM_BRU_CMPL);
+CACHE_EVENT_ATTR(branch-loads,            PM_BR_CMPL);
  CACHE_EVENT_ATTR(dTLB-load-misses,        PM_DTLB_MISS);
  CACHE_EVENT_ATTR(iTLB-load-misses,        PM_ITLB_MISS);

@@ -150,7 +150,7 @@ static struct attribute *power9_events_attr[] = {
      GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
      GENERIC_EVENT_PTR(PM_CMPLU_STALL),
      GENERIC_EVENT_PTR(PM_INST_CMPL),
-    GENERIC_EVENT_PTR(PM_BRU_CMPL),
+    GENERIC_EVENT_PTR(PM_BR_CMPL),
      GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
      GENERIC_EVENT_PTR(PM_LD_REF_L1),
      GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
@@ -167,7 +167,7 @@ static struct attribute *power9_events_attr[] = {
      CACHE_EVENT_PTR(PM_L2_ST_MISS),
      CACHE_EVENT_PTR(PM_L2_ST),
      CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
-    CACHE_EVENT_PTR(PM_BRU_CMPL),
+    CACHE_EVENT_PTR(PM_BR_CMPL),
      CACHE_EVENT_PTR(PM_DTLB_MISS),
      CACHE_EVENT_PTR(PM_ITLB_MISS),
      NULL
@@ -231,7 +231,7 @@ static int power9_generic_events_dd1[] = {
      [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =    PM_ICT_NOSLOT_CYC,
      [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =    PM_CMPLU_STALL,
      [PERF_COUNT_HW_INSTRUCTIONS] =            PM_INST_DISP,
-    [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =        PM_BRU_CMPL,
+    [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =        PM_BR_CMPL_ALT,
      [PERF_COUNT_HW_BRANCH_MISSES] =            PM_BR_MPRED_CMPL,
      [PERF_COUNT_HW_CACHE_REFERENCES] =        PM_LD_REF_L1,
      [PERF_COUNT_HW_CACHE_MISSES] =            PM_LD_MISS_L1_FIN,
@@ -242,7 +242,7 @@ static int power9_generic_events[] = {
      [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =    PM_ICT_NOSLOT_CYC,
      [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =    PM_CMPLU_STALL,
      [PERF_COUNT_HW_INSTRUCTIONS] =            PM_INST_CMPL,
-    [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =        PM_BRU_CMPL,
+    [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =        PM_BR_CMPL,
      [PERF_COUNT_HW_BRANCH_MISSES] =            PM_BR_MPRED_CMPL,
      [PERF_COUNT_HW_CACHE_REFERENCES] =        PM_LD_REF_L1,
      [PERF_COUNT_HW_CACHE_MISSES] =            PM_LD_MISS_L1_FIN,
@@ -368,7 +368,7 @@ static int 
power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
      },
      [ C(BPU) ] = {
          [ C(OP_READ) ] = {
-            [ C(RESULT_ACCESS) ] = PM_BRU_CMPL,
+            [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
              [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
          },
          [ C(OP_WRITE) ] = {
@@ -453,6 +453,10 @@ static int __init init_power9_pmu(void)
           * sampling scenarios in power9 DD1, instead use PM_INST_DISP.
           */
          EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP;
+        /*
+         * This is a hack, but then this is only for DD1
+         */
+        EVENT_VAR(PM_BR_CMPL, _g).id = PM_BR_CMPL_ALT;
          rc = register_power_pmu(&power9_isa207_pmu);
      } else {
          rc = register_power_pmu(&power9_pmu);