[RFC PATCH 5/7] powerpc/book3s: Don't turn on the MSR[ME] bit until opal processes the reason.

[Nicholas Piggin]

On Tue, 21 Feb 2017 07:22:56 +0530
Mahesh J Salgaonkar <mahesh at linux.vnet.ibm.com> wrote:

> From: Mahesh Salgaonkar <mahesh at linux.vnet.ibm.com>
> 
> Delay it until we are done with machine_check_early() call. Turn on MSR[ME]
> once opal is done with processing MCE.

Why? This seems like quite a regression -- the MCE handler today
has about 60 instructions and 30 l/st with ME clear.


> 
> Signed-off-by: Mahesh Salgaonkar <mahesh at linux.vnet.ibm.com>
> ---
>  arch/powerpc/kernel/exceptions-64s.S |   12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> index d39d611..fa768a7 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -238,6 +238,12 @@ BEGIN_FTR_SECTION
>  	std	r9,_CCR(r1)		/* Save CR in stackframe */
>  	/* Save r9 through r13 from EXMC save area to stack frame. */
>  	EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
> +	std	r0,GPR0(r1)	/* Save r0 */
> +	EXCEPTION_PROLOG_COMMON_3(0x200)
> +	bl	save_nvgprs
> +	addi	r3,r1,STACK_FRAME_OVERHEAD
> +	bl	machine_check_early
> +	std	r3,RESULT(r1)	/* Save result */
>  	mfmsr	r11			/* get MSR value */
>  	ori	r11,r11,MSR_ME		/* turn on ME bit */
>  	ori	r11,r11,MSR_RI		/* turn on RI bit */
> @@ -345,12 +351,6 @@ EXC_COMMON_BEGIN(machine_check_common)
>  	 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
>  	 */
>  EXC_COMMON_BEGIN(machine_check_handle_early)
> -	std	r0,GPR0(r1)	/* Save r0 */
> -	EXCEPTION_PROLOG_COMMON_3(0x200)
> -	bl	save_nvgprs
> -	addi	r3,r1,STACK_FRAME_OVERHEAD
> -	bl	machine_check_early
> -	std	r3,RESULT(r1)	/* Save result */
>  	ld	r12,_MSR(r1)
>  #ifdef	CONFIG_PPC_P7_NAP
>  	/*
>