[PATCH 4/4] powerpc/powernv: handle POWER9 machine checks
kbuild test robot
lkp at intel.com
Fri Feb 17 11:36:51 AEDT 2017
Hi Nicholas,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.10-rc8 next-20170216]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Nicholas-Piggin/POWER9-machine-check-handler/20170217-023423
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=powerpc
All errors (new ones prefixed by >>):
arch/powerpc/kernel/mce_power.c: In function 'mce_get_derror_p9':
arch/powerpc/kernel/mce_power.c:423:11: error: 'regs' undeclared (first use in this function)
*addr = regs->nip;
^~~~
arch/powerpc/kernel/mce_power.c:423:11: note: each undeclared identifier is reported only once for each function it appears in
arch/powerpc/kernel/mce_power.c: In function 'mce_get_ierror_p9':
arch/powerpc/kernel/mce_power.c:484:10: error: 'regs' undeclared (first use in this function)
*addr = regs->nip;
^~~~
arch/powerpc/kernel/mce_power.c: In function '__machine_check_early_realmode_p9':
arch/powerpc/kernel/mce_power.c:555:13: error: too few arguments to function 'mce_handle_derror_p9'
handled = mce_handle_derror_p9(regs);
^~~~~~~~~~~~~~~~~~~~
arch/powerpc/kernel/mce_power.c:376:12: note: declared here
static int mce_handle_derror_p9(struct pt_regs *regs, uint64_t *addr,
^~~~~~~~~~~~~~~~~~~~
arch/powerpc/kernel/mce_power.c:558:13: error: too few arguments to function 'mce_handle_ierror_p9'
handled = mce_handle_ierror_p9(regs);
^~~~~~~~~~~~~~~~~~~~
arch/powerpc/kernel/mce_power.c:398:12: note: declared here
static int mce_handle_ierror_p9(struct pt_regs *regs, uint64_t *addr,
^~~~~~~~~~~~~~~~~~~~
>> arch/powerpc/kernel/mce_power.c:550:21: error: unused variable 'initiator' [-Werror=unused-variable]
enum MCE_Initiator initiator = MCE_INITIATOR_CPU;
^~~~~~~~~
>> arch/powerpc/kernel/mce_power.c:549:20: error: unused variable 'severity' [-Werror=unused-variable]
enum MCE_Severity severity = MCE_SEV_ERROR_SYNC;
^~~~~~~~
cc1: all warnings being treated as errors
vim +/initiator +550 arch/powerpc/kernel/mce_power.c
370 handled = mce_handle_ue_error(regs);
371
372 save_mce_event(regs, handled, &mce_error_info, nip, addr);
373 return handled;
374 }
375
> 376 static int mce_handle_derror_p9(struct pt_regs *regs, uint64_t *addr,
377 enum MCE_Severity *severity, enum MCE_Initiator *initiator)
378 {
379 uint64_t dsisr = regs->dsisr;
380
381 #if 0
382 /* Could invalidate all tlbs then step over failing tlbie(l)? */
383 if (dsisr & P9_DSISR_MC_USER_TLBIE) {
384 regs->nip += 4;
385 dsisr &= ~P9_DSISR_MC_USER_TLBIE;
386 }
387 #endif
388
389 return mce_handle_flush_derrors(dsisr,
390 P9_DSISR_MC_SLB_PARITY_MFSLB |
391 P9_DSISR_MC_SLB_MULTIHIT_MFSLB,
392
393 P9_DSISR_MC_TLB_MULTIHIT_MFTLB,
394
395 P9_DSISR_MC_ERAT_MULTIHIT);
396 }
397
398 static int mce_handle_ierror_p9(struct pt_regs *regs, uint64_t *addr,
399 enum MCE_Severity *severity, enum MCE_Initiator *initiator)
400 {
401 uint64_t srr1 = regs->msr;
402
403 switch (P9_SRR1_MC_IFETCH(srr1)) {
404 case P9_SRR1_MC_IFETCH_SLB_PARITY:
405 case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
406 return mce_flush(MCE_FLUSH_SLB);
407 case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
408 return mce_flush(MCE_FLUSH_TLB);
409 case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
410 return mce_flush(MCE_FLUSH_ERAT);
411 default:
412 return 0;
413 }
414 }
415
416 static void mce_get_derror_p9(struct mce_error_info *mce_err,
417 uint64_t *addr, uint64_t dsisr)
418 {
419 mce_err->severity = MCE_SEV_ERROR_SYNC;
420 mce_err->initiator = MCE_INITIATOR_CPU;
421
422 if (dsisr & P9_DSISR_MC_USER_TLBIE)
423 *addr = regs->nip;
424 else
425 *addr = regs->dar;
426
427 if (dsisr & P9_DSISR_MC_UE) {
428 mce_err->error_type = MCE_ERROR_TYPE_UE;
429 mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
430 } else if (dsisr & P9_DSISR_MC_UE_TABLEWALK) {
431 mce_err->error_type = MCE_ERROR_TYPE_UE;
432 mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
433 } else if (dsisr & P9_DSISR_MC_LINK_LOAD_TIMEOUT) {
434 mce_err->error_type = MCE_ERROR_TYPE_LINK;
435 mce_err->u.link_error_type = MCE_LINK_ERROR_LOAD_TIMEOUT;
436 } else if (dsisr & P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT) {
437 mce_err->error_type = MCE_ERROR_TYPE_LINK;
438 mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT;
439 } else if (dsisr & P9_DSISR_MC_ERAT_MULTIHIT) {
440 mce_err->error_type = MCE_ERROR_TYPE_ERAT;
441 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
442 } else if (dsisr & P9_DSISR_MC_TLB_MULTIHIT_MFTLB) {
443 mce_err->error_type = MCE_ERROR_TYPE_TLB;
444 mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
445 } else if (dsisr & P9_DSISR_MC_USER_TLBIE) {
446 mce_err->error_type = MCE_ERROR_TYPE_USER;
447 mce_err->u.user_error_type = MCE_USER_ERROR_TLBIE;
448 } else if (dsisr & P9_DSISR_MC_SLB_PARITY_MFSLB) {
449 mce_err->error_type = MCE_ERROR_TYPE_SLB;
450 mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
451 } else if (dsisr & P9_DSISR_MC_SLB_MULTIHIT_MFSLB) {
452 mce_err->error_type = MCE_ERROR_TYPE_SLB;
453 mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
454 } else if (dsisr & P9_DSISR_MC_RA_LOAD) {
455 mce_err->error_type = MCE_ERROR_TYPE_RA;
456 mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD;
457 } else if (dsisr & P9_DSISR_MC_RA_TABLEWALK) {
458 mce_err->error_type = MCE_ERROR_TYPE_RA;
459 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
460 } else if (dsisr & P9_DSISR_MC_RA_TABLEWALK_FOREIGN) {
461 mce_err->error_type = MCE_ERROR_TYPE_RA;
462 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN;
463 } else if (dsisr & P9_DSISR_MC_RA_FOREIGN) {
464 mce_err->error_type = MCE_ERROR_TYPE_RA;
465 mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD_STORE_FOREIGN;
466 }
467 }
468
469 static void mce_get_ierror_p9(struct mce_error_info *mce_err,
470 uint64_t *addr, uint64_t srr1)
471 {
472 switch (P9_SRR1_MC_IFETCH(srr1)) {
473 case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
474 case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
475 mce_err->severity = MCE_SEV_FATAL;
476 break;
477 default:
478 mce_err->severity = MCE_SEV_ERROR_SYNC;
479 break;
480 }
481
482 mce_err->initiator = MCE_INITIATOR_CPU;
483
484 *addr = regs->nip;
485
486 switch (P9_SRR1_MC_IFETCH(srr1)) {
487 case P9_SRR1_MC_IFETCH_UE:
488 mce_err->error_type = MCE_ERROR_TYPE_UE;
489 mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
490 break;
491 case P9_SRR1_MC_IFETCH_SLB_PARITY:
492 mce_err->error_type = MCE_ERROR_TYPE_SLB;
493 mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
494 break;
495 case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
496 mce_err->error_type = MCE_ERROR_TYPE_SLB;
497 mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
498 break;
499 case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
500 mce_err->error_type = MCE_ERROR_TYPE_ERAT;
501 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
502 break;
503 case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
504 mce_err->error_type = MCE_ERROR_TYPE_TLB;
505 mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
506 break;
507 case P9_SRR1_MC_IFETCH_UE_TLB_RELOAD:
508 mce_err->error_type = MCE_ERROR_TYPE_UE;
509 mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
510 break;
511 case P9_SRR1_MC_IFETCH_LINK_TIMEOUT:
512 mce_err->error_type = MCE_ERROR_TYPE_LINK;
513 mce_err->u.link_error_type = MCE_LINK_ERROR_IFETCH_TIMEOUT;
514 break;
515 case P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT:
516 mce_err->error_type = MCE_ERROR_TYPE_LINK;
517 mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT;
518 break;
519 case P9_SRR1_MC_IFETCH_RA:
520 mce_err->error_type = MCE_ERROR_TYPE_RA;
521 mce_err->u.ra_error_type = MCE_RA_ERROR_IFETCH;
522 break;
523 case P9_SRR1_MC_IFETCH_RA_TABLEWALK:
524 mce_err->error_type = MCE_ERROR_TYPE_RA;
525 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH;
526 break;
527 case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
528 mce_err->error_type = MCE_ERROR_TYPE_RA;
529 mce_err->u.ra_error_type = MCE_RA_ERROR_STORE;
530 break;
531 case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
532 mce_err->error_type = MCE_ERROR_TYPE_LINK;
533 mce_err->u.link_error_type = MCE_LINK_ERROR_STORE_TIMEOUT;
534 break;
535 case P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN:
536 mce_err->error_type = MCE_ERROR_TYPE_RA;
537 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN;
538 break;
539 default:
540 break;
541 }
542 }
543
544 long __machine_check_early_realmode_p9(struct pt_regs *regs)
545 {
546 uint64_t nip, addr;
547 long handled;
548 struct mce_error_info mce_error_info = { 0 };
> 549 enum MCE_Severity severity = MCE_SEV_ERROR_SYNC;
> 550 enum MCE_Initiator initiator = MCE_INITIATOR_CPU;
551
552 nip = regs->nip;
553
554 if (P9_SRR1_MC_LOADSTORE(regs->msr)) {
555 handled = mce_handle_derror_p9(regs);
556 mce_get_derror_p9(&mce_error_info, &addr, regs->dsisr);
557 } else {
> 558 handled = mce_handle_ierror_p9(regs);
559 mce_get_ierror_p9(&mce_error_info, &addr, regs->msr);
560 }
561
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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