[PATCH 0/7] cxl: Add support for Coherent Accelerator Interface Architecture 2.0
clombard at linux.vnet.ibm.com
Thu Feb 2 04:30:06 AEDT 2017
This series adds support for a cxl card which supports the Coherent
Accelerator Interface Architecture 2.0.
It requires IBM Power9 system and the Power Service Layer, version 9.
The PSL provides the address translation and system memory cache for
CAIA compliant Accelerators.
the PSL attaches to the IBM Processor chip through the PCIe link using
the PSL-specific “CAPI Protocol” Transaction Layer Packets.
The PSL and CAPP communicate using PowerBus packets.
When using a PCIe link the PCIe Host Bridge (PHB) decodes the CAPI
Protocol Packets from the PSL and forwards them as PowerBus data
packets. The PSL also has an optional DMA feature which allows the AFU
to send native PCIe reads and writes to the Processor.
CAIA 2 introduces new features:
* There are several similarities among the two programming models:
Dedicated-Process and shared models.
* DMA support
* Nest MMU to handle translation addresses.
It builds on top of the existing cxl driver for the first version of
CAIA. Today only the bare-metal environment supports these new features.
Compatibility with the CAIA, version 1, allows applications and system
software to migrate from one implementation to another with minor
Most of the differences are:
* Power Service Layer registers: p1 and p2 registers. These new
registers require reworking The service layer API (in cxl.h).
* Support of Radix mode. Power9 consist of multiple memory management
model. So we need to select the right Translation mechanism mode.
* Dedicated-Shared Process Programming Model
* Process element entry. Structure cxl_process_element_common is
* Translation Fault Handling. Only a page fault is now handle by the
driver cxl when a translation fault is occurred.
Roughly 3/4 of the code is common between the two CAIA version. When
the code needs to call a specific implementation, it does so
through an API. The PSL8 and PSL9 implementations each describe
their own definition. See struct cxl_service_layer_ops.
The first 3 patches are mostly cleanup and fixes, separating the
psl8-specific code from the code which will also be used for psl9.
Patches 4 restructure existing code, to easily add the psl
Patch 5 and 6 rename and isolate implementation-specific code.
Patch 7 introduces the core of the PSL9-specific code.
Tested on Simulation environment.
Christophe Lombard (7):
cxl: Read vsec perst load image
cxl: Remove unused values in bare-metal environment.
cxl: Keep track of mm struct associated with a context
cxl: Update implementation service layer
cxl: Rename some psl8 specific functions
cxl: Isolate few psl8 specific calls
cxl: Add psl9 specific code
drivers/misc/cxl/api.c | 16 ++-
drivers/misc/cxl/context.c | 66 +++++++--
drivers/misc/cxl/cxl.h | 207 +++++++++++++++++++++++-----
drivers/misc/cxl/debugfs.c | 41 ++++--
drivers/misc/cxl/fault.c | 138 ++++++-------------
drivers/misc/cxl/file.c | 14 +-
drivers/misc/cxl/guest.c | 10 +-
drivers/misc/cxl/irq.c | 54 +++++++-
drivers/misc/cxl/native.c | 318 +++++++++++++++++++++++++++++++++++-------
drivers/misc/cxl/pci.c | 337 ++++++++++++++++++++++++++++++++++++++-------
drivers/misc/cxl/trace.h | 43 ++++++
11 files changed, 976 insertions(+), 268 deletions(-)
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