[PATCH v3 00/17] powerpc: Do alignment fixups using analyse_instr etc.

[Paul Mackerras]

This series extends the instruction emulation infrastructure in
arch/powerpc/lib/sstep.c and uses it for emulating instructions when
we get an alignment interrupt.  The advantage of this is that we only
have to add the new POWER9 instructions in one place, and it fixes
several bugs in alignment interrupt handling that have been identified
recently.

With this, analyse_instr() and emulate_step() handle almost all load
and store instructions in Power ISA v3.00 -- all except the atomic
memory operations (lwat, stwat, etc.).  We now always use the largest
possible aligned memory accesses (up to 8 bytes) to emulate unaligned
accesses.  If we get a fault, the faulting address is accurately
recorded in regs->dar.  We also can now access FP/VMX/VSX registers
directly if they are live, without having to spill them all to the
thread_struct and the reload them all later.  There are also various
other fixes in the series.

This version is based on the current powerpc next branch.

Paul.

 arch/powerpc/Kconfig                  |    4 -
 arch/powerpc/include/asm/ppc-opcode.h |   10 +-
 arch/powerpc/include/asm/sstep.h      |   90 +-
 arch/powerpc/kernel/align.c           |  774 +-----------
 arch/powerpc/lib/Makefile             |    3 +-
 arch/powerpc/lib/ldstfp.S             |  307 ++---
 arch/powerpc/lib/quad.S               |   62 +
 arch/powerpc/lib/sstep.c              | 2139 +++++++++++++++++++++++----------
 8 files changed, 1802 insertions(+), 1587 deletions(-)