[PATCH v2 0/10] powerpc: Beef up single-stepping/instruction emulation infrastructure

[Paul Mackerras]

This patch series extends the code in arch/powerpc/lib/sstep.c so that
it handles almost all load and store instructions -- all except the
atomic memory operations (lwat, stwat, etc.).  It also makes sure that
we use the largest possible aligned accesses to access memory and that
we don't access the CPU FP/VMX/VSX registers when they don't contain
user data.  With this, it should be possible to replace the body of
the alignment interrupt handler with a call to emulate_step() or
something quite similar.

This version is based on the powerpc tree next branch as of a day or
two ago, and includes code to emulate addpcis, a fix for the isel
emulation, code to handle the multi-register loads and stores in
little-endian mode, and a fix for the wrong behaviour in updating RA
for load/store with update instructions in 32-bit mode.

Paul.

 arch/powerpc/include/asm/sstep.h |   77 +-
 arch/powerpc/lib/Makefile        |    2 +-
 arch/powerpc/lib/ldstfp.S        |  307 ++----
 arch/powerpc/lib/quad.S          |   62 ++
 arch/powerpc/lib/sstep.c         | 1929 ++++++++++++++++++++++++++++----------
 5 files changed, 1654 insertions(+), 723 deletions(-)