[PATCH] cxl: Add support for POWER9 DD2

[Vaibhav Jain]

Hi Christophe,

Christophe Lombard <clombard at linux.vnet.ibm.com> writes:
> +	/* For debugging with trace arrays */
> +	/* Configure RX trace 0 segmented mode */
> +	cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000000ULL);
> +	/* Configure RX trace 1 segmented mode */
> +	cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xAA00000000000001ULL);
> +	/* Configure CT trace 0 segmented mode */
> +	cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xA2B8000000000003ULL);
> +	/* Configure LA0 trace 0 segmented mode */
> +	cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x83FFC00000000005ULL);
> +	/* Configure JM0 trace 0 segmented mode */
> +	cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000007ULL);
> +	/* Configure DMA trace 0 segmented mode */
> +	cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000008ULL);
> +	/* Configure DMA trace 1 segmented mode */
> +	cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000009ULL);
Please wrap this block that configures the trace arrays in #ifdef
DEBUG. Or it will be better if we remove it from here as the register is
already accessible via debugfs.

---
Vaibhav Jain <vaibhav at linux.vnet.ibm.com>
Linux Technology Center, IBM India Pvt. Ltd.