[PATCH v2] Fix buglet in tlbiel where we set L=1 for ISA 206/7

[Balbir Singh]

This patch fixes a bug where we set bit 10 in tlbie via our
custom .long opcode for tlbiel. These bits are reserved for
2.06/2.07. In ISA 3.0 bit 10 is a part of the register field
RS and we could end up corrupting the meaning of the register
field completely with L=1

Signed-off-by: Balbir Singh <bsingharora at gmail.com>
---
 Changelog v2->v1:
	Use the compiler to generate tlbiel as suggsted by mpe
	Drop the rest of the changes to macros

 arch/powerpc/mm/hash_native_64.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 0e4e965..0f77edf 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -123,8 +123,9 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
 		va |= ssize << 8;
 		sllp = get_sllp_encoding(apsize);
 		va |= sllp << 5;
-		asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
-			     : : "r"(va) : "memory");
+		asm volatile(ASM_FTR_IFCLR("tlbiel %0,0", "tlbiel %0", %1)
+			     : : "r" (va), "i" (CPU_FTR_ARCH_206)
+			     : "memory");
 		break;
 	default:
 		/* We need 14 to 14 + i bits of va */
@@ -141,8 +142,9 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
 		 */
 		va |= (vpn & 0xfe);
 		va |= 1; /* L */
-		asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
-			     : : "r"(va) : "memory");
+		asm volatile(ASM_FTR_IFCLR("tlbiel %0,1", "tlbiel %0", %1)
+			     : : "r" (va), "i" (CPU_FTR_ARCH_206)
+			     : "memory");
 		break;
 	}
 
-- 
2.5.5