[PATCH v3 6/6] powerpc/mm: Batch tlb flush when invalidating pte entries
Aneesh Kumar K.V
aneesh.kumar at linux.vnet.ibm.com
Tue Nov 22 13:21:38 AEDT 2016
Benjamin Herrenschmidt <benh at kernel.crashing.org> writes:
> On Tue, 2016-11-22 at 00:03 +0530, Aneesh Kumar K.V wrote:
>> + /*
>> + * If we are trying to clear the pte, we can skip
>> + * the below sequence and batch the tlb flush. The
>> + * tlb flush batching is done by mmu gather code
>> + */
>> + if (new_pte) {
>> + asm volatile("ptesync" : : : "memory");
>> + psize = radix_get_mmu_psize(pg_sz);
>> + radix__flush_tlb_page_psize(mm, addr, psize);
>> + __radix_pte_update(ptep, 0, new_pte);
>> + }
>> } else
>> old_pte = __radix_pte_update(ptep, clr, set);
>
> Can you check the valid bit ? What if we are just setting a swap PTE
> on top of an invalid one for example ?
>
> Should the above case be limited to both old and new being valid ?
We should use set_pte_at if the old pte is not valid and that doesn't
involve a tlb flush.
-aneesh
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