[PATCH v8 10/11] cpuidle/powernv: Add support for POWER ISA v3 idle states

[Michael Ellerman]

"Shreyas B. Prabhu" <shreyas at linux.vnet.ibm.com> writes:

> POWER ISA v3 defines a new idle processor core mechanism. In summary,
>  a) new instruction named stop is added.
>  b) new per thread SPR named PSSCR is added which controls the behavior
> 	of stop instruction.
>
> Supported idle states and value to be written to PSSCR register to enter
> any idle state is exposed via ibm,cpu-idle-state-names and
> ibm,cpu-idle-state-psscr respectively. To enter an idle state,
> platform provided power_stop() needs to be invoked with the appropriate
> PSSCR value.
>
> This patch adds support for this new mechanism in cpuidle powernv driver.
>
> Cc: Rafael J. Wysocki <rafael.j.wysocki at intel.com>
> Cc: Daniel Lezcano <daniel.lezcano at linaro.org>
> Cc: Rob Herring <robh+dt at kernel.org>
> Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi at arm.com>
> Cc: linux-pm at vger.kernel.org

Rafael/Daniel do you guys want to ack or nack this?

I'll take silence as "not bothered" and merge the whole series via the
powerpc tree.

cheers