[v6] powerpc/timer - large decrementer support

[Michael Ellerman]

On Fri, 2016-01-07 at 06:20:39 UTC, Oliver O'Halloran wrote:
> Power ISAv3 adds a large decrementer (LD) mode which increases the size
> of the decrementer register. The size of the enlarged decrementer
> register is between 32 and 64 bits with the exact size being dependent
> on the implementation. When in LD mode, reads are sign extended to 64
> bits and a decrementer exception is raised when the high bit is set (i.e
> the value goes below zero). Writes however are truncated to the physical
> register width so some care needs to be taken to ensure that the high
> bit is not set when reloading the decrementer. This patch adds support
> for using the LD inside the host kernel on processors that support it.
> 
> When LD mode is supported firmware will supply the ibm,dec-bits property
> for CPU nodes to allow the kernel to determine the maximum decrementer
> value. Enabling LD mode is a hypervisor privileged operation so the kernel
> can only enable it manually when running in hypervisor mode. Guests that
> support LD mode can request it using the "ibm,client-architecture-support"
> firmware call (not implemented in this patch) or some other platform
> specific method. If this property is not supplied then the traditional
> decrementer width of 32 bit is assumed and LD mode will not be enabled.
> 
> This patch was based on initial work by Jack Miller.
> 
> Signed-off-by: Oliver O'Halloran <oohall at gmail.com>
> Signed-off-by: Balbir Singh <bsingharora at gmail.com>
> Acked-by: Michael Neuling <mikey at neuling.org>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/799010244685334b34e674d354

cheers