[PATCH] powerpc/xics: Properly set Edge/Level type and enable resend

[Michael Ellerman]

Benjamin Herrenschmidt <benh at kernel.crashing.org> writes:

> This sets the type of the interrupt appropriately. We set it as follow:
>
>  - If not mapped from the device-tree, we use edge. This is the case
> of the virtual interrupts and PCI MSIs for example.
>
>  - If mapped from the device-tree and #interrupt-cells is 2 (PAPR
> compliant), we use the second cell to set the appropriate type
>
>  - If mapped from the device-tree and #interrupt-cells is 1 (current
> OPAL on P8 does that), we assume level sensitive since those are
> typically going to be the PSI LSIs which are level sensitive.
>
> Additionally, we mark the interrupts requested via the opal_interrupts
> property all level. This is a bit fishy but the best we can do until we
> fix OPAL to properly expose them with a complete descriptor. It is also
> correct for the current HW anyway as OPAL interrupts are currently PCI
> error and PSI interrupts which are level.
>
> Finally now that edge interrupts are properly identified, we can enable
> CONFIG_HARDIRQS_SW_RESEND which will make the core re-send them if
> they occur while masked, which some drivers rely upon.
>
> This fixes issues with lost interrupts on some Mellanox adapters.
>
> Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>

Broken since forever?

Cc stable?

cheers