[PATCH] cxl: Increase timeout for detection of AFU mmio hang

[Frederic Barrat]

Received privately:
Tested-by: Frank Haverkamp <haver at linux.vnet.ibm.com>


Le 19/04/2016 18:34, Frederic Barrat a écrit :
> PSL designers recommend a larger value for the mmio hang pulse, 256 us
> instead of 1 us. The CAIA architecture states that it needs to be
> smaller than 1/2 of the RTOS timeout set in the PHB for outbound
> non-posted transactions, which is still (easily) the case here.
>
> Signed-off-by: Frederic Barrat <fbarrat at linux.vnet.ibm.com>
> ---
> Needs to be applied on top of http://patchwork.ozlabs.org/patch/604029/
>
>
>   drivers/misc/cxl/pci.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index 94fd3f7..0a9c15b 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -375,8 +375,10 @@ static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev
>   		return -ENODEV;
>   	}
>
> +	psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
> +	psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
>   	/* Tell PSL where to route data to */
> -	psl_dsnctl = 0x0000900002000000ULL | (chipid << (63-5));
> +	psl_dsnctl |= (chipid << (63-5));
>   	psl_dsnctl |= (capp_unit_id << (63-13));
>
>   	cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
>