[PATCH 0/8] FP/VEC/VSX switching optimisations

[David Laight]

From: Cyril Bur
> Sent: 18 November 2015 03:27
...
> The goal of these patches is to rework how the 'math' registers (FP, VEC
> and VSX) are context switched. Currently the kernel adopts a lazy approach,
> always switching userspace tasks with all three facilities disabled and
> loads in each set of registers upon receiving each unavailable exception.
> The kernel does try to avoid disabling the features in the syscall quick
> path but it during testing it appears that even what should be a simple
> syscall still causes the kernel to use some facilities (vectorised memcpy
> for example) for its self and therefore disable it for the user task.

Perhaps the kernel should be avoiding using these registers?
I wonder if the gain from using vectorised memcpy is typically
enough to warrant the cost of the save and restore?

There may even be scope for kernel code doing a save/restore
of a small number of registers onto an in-stack save area.
It would need to be linked to the data of the thread
that owns the fpu registers so that a save request could
be honoured.
Pre-emption would probably need to be disabled, but nested
use, and use from ISR should be ok.

	David