[PATCH 2/4] perf: jevents: Program to convert JSON file to C style file

[Andi Kleen]

> So instead of this flat structure, there should at minimum be broad categorization 
> of the various parts of the hardware they relate to: whether they relate to the 
> branch predictor, memory caches, TLB caches, memory ops, offcore, decoders, 
> execution units, FPU ops, etc., etc. - so that they can be queried via 'perf 
> list'.

The categorization is generally on the stem name, which already works fine with
the existing perf list wildcard support. So for example you only want 
branches. 

perf list br*
...
  br_inst_exec.all_branches                         
       [Speculative and retired branches]
  br_inst_exec.all_conditional                      
       [Speculative and retired macro-conditional branches]
  br_inst_exec.all_direct_jmp                       
       [Speculative and retired macro-unconditional branches excluding calls and indirects]
  br_inst_exec.all_direct_near_call                 
       [Speculative and retired direct near calls]
  br_inst_exec.all_indirect_jump_non_call_ret       
       [Speculative and retired indirect branches excluding calls and returns]
  br_inst_exec.all_indirect_near_return             
       [Speculative and retired indirect return branches]
...

Or mid level cache events:

perf list l2*
...
  l2_l1d_wb_rqsts.all                               
       [Not rejected writebacks from L1D to L2 cache lines in any state]
  l2_l1d_wb_rqsts.hit_e                             
       [Not rejected writebacks from L1D to L2 cache lines in E state]
  l2_l1d_wb_rqsts.hit_m                             
       [Not rejected writebacks from L1D to L2 cache lines in M state]
  l2_l1d_wb_rqsts.miss                              
       [Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)]
  l2_lines_in.all                                   
       [L2 cache lines filling L2]
...

There are some exceptions, but generally it works this way.

The stem could be put into a separate header, but it would seem redundant to me. 

> We don't just want the import the unstructured mess that these event files are - 
> we want to turn them into real structure. We can still keep the messy vendor names 
> as well, like IDQ.DSB_CYCLES, but we want to impose structure as well.

The vendor names directly map to the micro architecture, which is whole
point of the events. IDQ is a part of the CPU, and is described in the 
CPU manuals. One of the main motivations for adding event lists is to make
perf match to that documentation.

> 
> 3)
> 
> There should be good 'perf list' visualization for these events: grouping, 
> individual names, with a good interface to query details if needed. I.e. it should 
> be possible to browse and discover events relevant to the CPU the tool is 
> executing on.

I suppose we could change perf list to give the stem names as section headers
to make the long list a bit more readable.

Generally you need to have some knowledge of the micro architecture to use
these events. There is no way around that.

-Andi
-- 
ak at linux.intel.com -- Speaking for myself only