[alsa-devel] [PATCH] ASoC: fsl_spdif: Don't try to round-up for clock divisor calculation
nicoleotsuka at gmail.com
Wed May 27 09:00:49 AEST 2015
On Tue, May 26, 2015 at 07:02:48PM +0800, Zidan Wang wrote:
> On Mon, May 25, 2015 at 08:24:25AM -0700, Nicolin Chen wrote:
> > On Mon, May 25, 2015 at 12:13:45PM -0300, Fabio Estevam wrote:
> > > Hi Nicolin,
> > >
> > > On Mon, May 25, 2015 at 12:11 PM, Nicolin Chen <nicoleotsuka at gmail.com> wrote:
> > >
> > > > Hi Mark,
> > > >
> > > > Is that possible for you to provisionally revert this patch?
> > > > I wanted to wait for the test result from Fabio or Zidan in
> > > > the Cc list because I don't have a test environment for SPDIF
> > > > even though this change seems to make sense.
> > >
> > > I currently don't have access to a SPDIF receiver to test it.
> > Okay, let's wait for Zidan then. We only need to test the
> > playback route of supporting sample rates.
> I don't have the board which supported by community to test spdif out. So i used the imx7 board
i.MX6 ARM2, the one with the square green base board, should work,
although you may add some device nodes in dts to make it work.
> and test it with internal branch.
> I found that (txclk_df + 1) is better than txclk_df.
> I suspect the patch for clk_round_rate() is not in our branch. Could you please tell me which
> patch is for clk_round_rate? I want to cherry-pick it to our branch and test it.
Here is commit logs for the clock driver. You can check git-log of
your local one and cherry-pick those incremental patches. Another
clue is that after updating the clock driver to the latest version,
SSI master mode in your local branch would become abnormal since
it's still using pm + 2 to round the calculation.
Thanks a lot
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