[PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling

[Paul Mackerras]

On Wed, May 20, 2015 at 05:35:08PM -0500, Scott Wood wrote:
> 
> It's nominally a 64-bit register, but the upper 32 bits are reserved in
> ISA 2.06.  Do newer ISAs or certain implementations define things in the
> upper 32 bits, or is this just about the asm accesses being wrong on
> big-endian?

It's primarily about the asm accesses being wrong.

Paul.