[PATCH RESEND v6 1/2] arm64: dts: Add the arasan sdhci nodes in apm-storm.dtsi
Suman Tripathi
stripathi at apm.com
Tue May 12 15:33:46 AEST 2015
Hi ,
On Mon, May 11, 2015 at 2:08 PM, Suman Tripathi <stripathi at apm.com> wrote:
> This patch adds the arasan sdhci nodes to reuse the of-arasan
> driver for APM X-Gene SoC.
>
> Signed-off-by: Suman Tripathi <stripathi at apm.com>
> ---
> arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
> arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +++++++++++++++++++++++++++++++++
> 2 files changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts
> index 83578e7..7ccd517 100644
> --- a/arch/arm64/boot/dts/apm/apm-mustang.dts
> +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts
> @@ -52,3 +52,7 @@
> &xgenet {
> status = "ok";
> };
> +
> +&sdhci0 {
> + status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> index c8d3e0e..b5d2698 100644
> --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
> +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> @@ -145,6 +145,40 @@
> clock-output-names = "socplldiv2";
> };
>
> + ahbclk: ahbclk at 1f2ac000 {
> + compatible = "apm,xgene-device-clock";
> + #clock-cells = <1>;
> + clocks = <&socplldiv2 0>;
> + reg = <0x0 0x1f2ac000 0x0 0x1000
> + 0x0 0x17000000 0x0 0x2000>;
> + reg-names = "csr-reg", "div-reg";
> + csr-offset = <0x0>;
> + csr-mask = <0x1>;
> + enable-offset = <0x8>;
> + enable-mask = <0x1>;
> + divider-offset = <0x164>;
> + divider-width = <0x5>;
> + divider-shift = <0x0>;
> + clock-output-names = "ahbclk";
> + };
> +
> + sdioclk: sdioclk at 1f2ac000 {
> + compatible = "apm,xgene-device-clock";
> + #clock-cells = <1>;
> + clocks = <&socplldiv2 0>;
> + reg = <0x0 0x1f2ac000 0x0 0x1000
> + 0x0 0x17000000 0x0 0x2000>;
> + reg-names = "csr-reg", "div-reg";
> + csr-offset = <0x0>;
> + csr-mask = <0x2>;
> + enable-offset = <0x8>;
> + enable-mask = <0x2>;
> + divider-offset = <0x178>;
> + divider-width = <0x8>;
> + divider-shift = <0x0>;
> + clock-output-names = "sdioclk";
> + };
> +
> qmlclk: qmlclk {
> compatible = "apm,xgene-device-clock";
> #clock-cells = <1>;
> @@ -533,6 +567,15 @@
> interrupts = <0x0 0x4f 0x4>;
> };
>
> + sdhci0: sdhci at 1c000000 {
> + compatible = "arasan,sdhci-4.9a";
> + reg = <0x0 0x1c000000 0x0 0x100>;
> + interrupts = <0x0 0x49 0x4>;
> + dma-coherent;
> + clock-names = "clk_xin", "clk_ahb";
> + clocks = <&sdioclk 0>, <&ahbclk 0>;
> + };
> +
> phy1: phy at 1f21a000 {
> compatible = "apm,xgene-phy";
> reg = <0x0 0x1f21a000 0x0 0x100>;
> --
> 1.8.2.1
>
Can anyone from dt community review this patch ? I have changed the dts node
names from sdhc to sdhci as per Arnd, Michael comments .
--
Thanks,
with regards,
Suman Tripathi
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