[PATCH v3 1/3] arm64: dts: Add the arasan sdhc nodes in apm-storm.dtsi.

[Suman Tripathi]

Hi,

On Mon, May 4, 2015 at 11:33 AM, Michal Simek <michal.simek at xilinx.com> wrote:
> On 05/01/2015 06:54 AM, Suman Tripathi wrote:
>> This patch adds the arasan sdhc nodes to reuse the of-arasan
>> driver for APM X-Gene SoC.
>>
>> Signed-off-by: Suman Tripathi <stripathi at apm.com>
>> ---
>>  arch/arm64/boot/dts/apm-mustang.dts |  4 ++++
>>  arch/arm64/boot/dts/apm-storm.dtsi  | 44 +++++++++++++++++++++++++++++++++++++
>>  2 files changed, 48 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts
>> index 8eb6d94..d0e52a9 100644
>> --- a/arch/arm64/boot/dts/apm-mustang.dts
>> +++ b/arch/arm64/boot/dts/apm-mustang.dts
>> @@ -44,3 +44,7 @@
>>  &xgenet {
>>       status = "ok";
>>  };
>> +
>> +&sdhc0 {
>> +     status = "ok";
>> +};
>> diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
>> index 87d3205..d6c2216 100644
>> --- a/arch/arm64/boot/dts/apm-storm.dtsi
>> +++ b/arch/arm64/boot/dts/apm-storm.dtsi
>> @@ -144,6 +144,40 @@
>>                               clock-output-names = "socplldiv2";
>>                       };
>>
>> +                     ahbclk: ahbclk at 1f2ac000 {
>> +                             compatible = "apm,xgene-device-clock";
>> +                             #clock-cells = <1>;
>> +                             clocks = <&socplldiv2 0>;
>> +                             reg = <0x0 0x1f2ac000 0x0 0x1000
>> +                                     0x0 0x17000000 0x0 0x2000>;
>> +                             reg-names = "csr-reg", "div-reg";
>> +                             csr-offset = <0x0>;
>> +                             csr-mask = <0x1>;
>> +                             enable-offset = <0x8>;
>> +                             enable-mask = <0x1>;
>> +                             divider-offset = <0x164>;
>> +                             divider-width = <0x5>;
>> +                             divider-shift = <0x0>;
>> +                             clock-output-names = "ahbclk";
>> +                     };
>> +
>> +                     sdioclk: sdioclk at 1f2ac000 {
>> +                             compatible = "apm,xgene-device-clock";
>> +                             #clock-cells = <1>;
>> +                             clocks = <&socplldiv2 0>;
>> +                             reg = <0x0 0x1f2ac000 0x0 0x1000
>> +                                     0x0 0x17000000 0x0 0x2000>;
>> +                             reg-names = "csr-reg", "div-reg";
>> +                             csr-offset = <0x0>;
>> +                             csr-mask = <0x2>;
>> +                             enable-offset = <0x8>;
>> +                             enable-mask = <0x2>;
>> +                             divider-offset = <0x178>;
>> +                             divider-width = <0x8>;
>> +                             divider-shift = <0x0>;
>> +                             clock-output-names = "sdioclk";
>> +                     };
>> +
>>                       qmlclk: qmlclk {
>>                               compatible = "apm,xgene-device-clock";
>>                               #clock-cells = <1>;
>> @@ -503,6 +537,16 @@
>>                       interrupts = <0x0 0x4f 0x4>;
>>               };
>>
>> +             sdhc0: sdhc at 1c000000 {
>> +                     device_type = "sdhc";
>> +                     compatible = "arasan,sdhci-8.9a", "arasan,sdhci-4.9a";
>
> I would just add 4.9a here because you want to use that quirks. We can
> add some quirks to 8.9a version if any new problem arises.

Make sense too. Our's is 4.9a. Thanks for the catch.

>
> Thanks,
> Michal



-- 
Thanks,
with regards,
Suman Tripathi