[PATCH] powerpc/fsl-pci: fix pcie range issue for some P1/P2 boards

[Scott Wood]

On Wed, 2015-07-22 at 18:08 +0800, Zhiqiang Hou wrote:

> From: Hou Zhiqiang <B48286 at freescale.com>

You CCed this to 
b21284 at freescale.com.  Who is that?  It would be nice to use "friendly" 
e-mail addresses, but at least include the name along with the e-mail address.

I suggest CCing the people who added these device trees.

> Impact board list:
> P1020MBG-PC. P1022DS, P2020RDB
> All above boards have its PCIE memory range less than 0xbfff_ffff,

If you mean that the physical address of the memory region is <= 0xbfff_ffff, 
I don't see the relevance.

> but in dts its boundary value was 0xe0000000. Both of them was maped
> to the same boundary 0xe0000000 which was Overlapped and crossed.

By "boundary" do you mean the PCIe bus address?  Why is it a problem for 
these independent PCIe root complexes to have the same PCIe bus addresses?

>  Cpu will access the illicit memery addr and detect error then lead to
> cpu stall.  So update dts for these boards.

What is illicit about it?

Why isn't the problem seen in the 36-bit device trees, which do the same 
thing?

-Scott