[PATCH 0/2] powerpc/powernv: Avoid compound PE for VF

Gavin Shan gwshan at linux.vnet.ibm.com
Fri Jul 17 10:14:41 AEST 2015

When the VF BAR size is equal to 128MB or bigger than that, the IOV BAR
is extended to cover number of maximal VFs supported by the PF, not 256.
Also, one PHB's M64 BAR is picked to cover VF BARs for 4 continous VFs,
but the PHB's M64 BAR is configured as being owned by single PE. Eventually,
those 4 VFs have 4 separate PEs from the perspective of PCI config or DMA,
but single shared PE from MMIO's perspective. Once we have compound PE, all
those 4 VFs included in the compound PE can't be passed to separate guests
with VFIO infrastructure.

The above gate (128MB) was choosen based on the assumption: one IOV BAR can
consume 1/4 of PHB's M64 window, which is 16GB. However, it can consume as
much as half of that (32GB) when the PF seats behind the root port. Accordingly,
the gate can be doubled to be 256MB in order to avoid compound PE as we can.

Gavin Shan (2):
  powerpc/powernv: Fix alignment for IOV BAR
  powerpc/powernv: Double VF BAR size for compound PE

 arch/powerpc/platforms/powernv/pci-ioda.c | 56 +++++++++++++++++++++++++------
 1 file changed, 45 insertions(+), 11 deletions(-)


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