[PATCH 2/2] powerpc/kexec: Reset HILE before kexec_sequence
stewart at linux.vnet.ibm.com
Wed Jul 8 16:14:22 AEST 2015
Samuel Mendoza-Jonas <sam.mj at au1.ibm.com> writes:
> On powernv secondary cpus are returned to OPAL, and will then enter the
> target kernel in big-endian. However if it is set the HILE bit will persist,
> causing the first exception in the target kernel to be delivered in
> litte-endian regardless of the kernel endianess.
> Make sure that the HILE bit is switched off before entering
> Signed-off-by: Samuel Mendoza-Jonas <sam.mj at au1.ibm.com>
Discussed with Sam on IRC, this makes kexec environment the same (or at
least closer to) booting the initial payload, which is a Good Thing(TM).
The ignoring of any error from opal_reinit_cpus() (as done in this
patch) is probably a good idea as we're either running on old firmware
which doesn't have the call (in which case we'd explode no matter what)
or we're on some crazy theoretical chip that doesn't do HILE=0, in which
case this gives us the best chance for compatibility.
Reviewed-by: Stewart Smith <stewart at linux.vnet.ibm.com>
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