[PATCH v1 0/3] SHA256 for PPC/SPE

[Markus Stockhausen]

[PATCH v1 0/3] SHA256 for PPC/SPE

The following patches add support for SIMD accelerated SHA256 
calculation on PPC processors with SPE instruction set. The 
implementation takes care of the following constraints:

- independant of processor endianess
- fallback to generic code if called from interrupt context
- disable preemtion only for short intervals

Performance numbers from insmod tcrypt sec=3 mode=304 taken
on e500v2 800 MHz (TP Link WDR4900)

data    per      generic     this patch  speedup  cycles
length  update   bytes/sec   bytes/sec   factor   per byte
------  -------  ----------  ----------  -------  --------
    16       16   5,558,336   8,248,272	  x1.48      96.99
    64       16  10,730,602  14,872,789   x1.38      53.79
    64       64  12,841,621  19,268,885   x1.50      41.52
   256       16  16,223,317  21,295,957   x1.31      37.57
   256       64  21,135,957  30,941,696   x1.46      25,86
   256      256	 22,664,448  35,765,845   x1.57      22,37
  1024       16  18,608,128  23,893,674   x1.28      33.48
  1024      256  27,427,840  43,427,498   x1.58      18.42
  1024     1024  28,064,768  45,659,136   x1.62      17.52
  2048       16  19,054,592  24,425,130   x1.28      32.75
  2048      256  28,435,797  45,087,402   x1.58      17.74
  2048     1024  29,091,157  47,395,498   x1.62      16.88
  2048     2048  29,225,642  47,756,629   x1.63      16.75
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