[PATCH v3 1/6] powerpc/mm: any thread in one core can be the first to setup TLB1
Chenhui Zhao
chenhui.zhao at freescale.com
Wed Dec 2 22:04:03 AEDT 2015
Hi Scott,
Any comment on these pathes?
Thanks,
Chenhui
On Fri, Nov 20, 2015 at 5:13 PM, Chenhui Zhao
<chenhui.zhao at freescale.com> wrote:
> On e6500, in the case of cpu hotplug, either thread in one core
> may be the first thread initilzing the TLB1. The subsequent threads
> must not setup it again.
>
> The code is derived from the comment of Scott Wood.
>
> Signed-off-by: Chenhui Zhao <chenhui.zhao at freescale.com>
> ---
> arch/powerpc/include/asm/cputhreads.h | 7 +++++++
> arch/powerpc/mm/tlb_nohash.c | 4 +---
> 2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cputhreads.h
> b/arch/powerpc/include/asm/cputhreads.h
> index ba42e46..b56cece 100644
> --- a/arch/powerpc/include/asm/cputhreads.h
> +++ b/arch/powerpc/include/asm/cputhreads.h
> @@ -94,6 +94,13 @@ static inline int cpu_last_thread_sibling(int cpu)
> return cpu | (threads_per_core - 1);
> }
>
> +static inline u32 get_tensr(void)
> +{
> + if (cpu_has_feature(CPU_FTR_SMT))
> + return mfspr(SPRN_TENSR);
> + else
> + return 1;
> +}
>
>
> #endif /* _ASM_POWERPC_CPUTHREADS_H */
> diff --git a/arch/powerpc/mm/tlb_nohash.c
> b/arch/powerpc/mm/tlb_nohash.c
> index bb04e4d..f466848 100644
> --- a/arch/powerpc/mm/tlb_nohash.c
> +++ b/arch/powerpc/mm/tlb_nohash.c
> @@ -640,9 +640,7 @@ static void early_init_this_mmu(void)
> * transient mapping would cause problems.
> */
> #ifdef CONFIG_SMP
> - if (cpu != boot_cpuid &&
> - (cpu != cpu_first_thread_sibling(cpu) ||
> - cpu == cpu_first_thread_sibling(boot_cpuid)))
> + if (hweight32(get_tensr()) > 1)
> map = false;
> #endif
>
> --
> 1.9.1
>
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