[PATCH v3 6/6] powerpc/powernv: allocate sparse PE# when using M64 BAR in Single PE mode

[Alexey Kardashevskiy]

On 08/14/2015 11:03 AM, Gavin Shan wrote:
> On Thu, Aug 13, 2015 at 10:11:11PM +0800, Wei Yang wrote:
>> When M64 BAR is set to Single PE mode, the PE# assigned to VF could be
>> sparse.
>>
>> This patch restructures the patch to allocate sparse PE# for VFs when M64
>> BAR is set to Single PE mode.
>>
>> Signed-off-by: Wei Yang <weiyang at linux.vnet.ibm.com>
>> ---
>> arch/powerpc/include/asm/pci-bridge.h     |    2 +-
>> arch/powerpc/platforms/powernv/pci-ioda.c |   59 +++++++++++++++++++----------
>> 2 files changed, 41 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
>> index 9d33ada..b026ef8 100644
>> --- a/arch/powerpc/include/asm/pci-bridge.h
>> +++ b/arch/powerpc/include/asm/pci-bridge.h
>> @@ -214,7 +214,7 @@ struct pci_dn {
>> #ifdef CONFIG_PCI_IOV
>> 	u16     vfs_expanded;		/* number of VFs IOV BAR expanded */
>> 	u16     num_vfs;		/* number of VFs enabled*/
>> -	int     offset;			/* PE# for the first VF PE */
>> +	int     pe_num_map[MAX_M64_BAR];/* PE# for the first VF PE or array */
>
> Same question as to "m64_map". pdn for non-PF doesn't need it.


non-PF is VF, right?




-- 
Alexey