[PATCH 3/3] powerpc/e6500: hw tablewalk: order the memory access when acquire/release tcd lock
haokexin at gmail.com
Thu Aug 13 21:51:37 AEST 2015
I didn't find anything unusual. But I think we do need to order the
load/store of esel_next when acquire/release tcd lock. For acquire,
add a data dependency to order the loads of lock and esel_next.
For release, even there already have a "isync" here, but it doesn't
guarantee any memory access order. So we still need "lwsync" for
the two stores for lock and esel_next.
Signed-off-by: Kevin Hao <haokexin at gmail.com>
arch/powerpc/mm/tlb_low_64e.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index e4185581c5a7..964754911987 100644
@@ -334,6 +334,8 @@ BEGIN_FTR_SECTION /* CPU_FTR_SMT */
* with tlbilx before overwriting.
+ andi r15,r15,0 /* add a data dependency to order the loards */
+ add r11,r11,r15 /* between the lock and esel_next */
@@ -447,6 +449,7 @@ BEGIN_FTR_SECTION
beq cr1,1f /* no unlock if lock was recursively grabbed */
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