[PATCH] powerpc/dts: Update the core cluster PLL node(s)

[Igal.Liberman at freescale.com]

Regards,
Igal Liberman.

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Tuesday, April 14, 2015 11:23 PM
> To: Liberman Igal-B31950
> Cc: devicetree at vger.kernel.org; linuxppc-dev at lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/dts: Update the core cluster PLL node(s)
> 
> On Tue, 2015-04-14 at 15:21 -0500, Scott Wood wrote:
> > On Tue, 2015-04-14 at 12:55 +0300, Igal.Liberman wrote:
> > > From: Igal Liberman <Igal.Liberman at freescale.com>
> > >
> > > This patch replaces the following:
> > > 	https://patchwork.ozlabs.org/patch/427664/
> > >
> > > This patch is described by the following binding document update:
> > > 	https://patchwork.ozlabs.org/patch/461150/
> > >
> > > Signed-off-by: Igal Liberman <Igal.Liberman at freescale.com>
> > > ---
> > >  arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi |    6 ++++--
> > >  1 file changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
> > > b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
> > > index 48e0b6e..7e1f074 100644
> > > --- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
> > > +++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
> > > @@ -49,14 +49,16 @@ global-utilities at e1000 {
> > >  		reg = <0x800 0x4>;
> > >  		compatible = "fsl,qoriq-core-pll-2.0";
> > >  		clocks = <&sysclk>;
> > > -		clock-output-names = "pll0", "pll0-div2", "pll0-div4";
> > > +		clock-output-names = "pll0", "pll0-div2", "pll0-div3",
> > > +				      "pll0-div4";
> > >  	};
> > >  	pll1: pll1 at 820 {
> > >  		#clock-cells = <1>;
> > >  		reg = <0x820 0x4>;
> > >  		compatible = "fsl,qoriq-core-pll-2.0";
> > >  		clocks = <&sysclk>;
> > > -		clock-output-names = "pll1", "pll1-div2", "pll1-div4";
> > > +		clock-output-names = "pll1", "pll1-div2", "pll1-div3",
> > > +				      "pll1-div4";
> >
> > Wait, so if the driver implements the binding you submitted, you'll
> > break compatibility with these older device trees...
> >
> > I think we need to just accept the ugly count-the-clock-names approach
> > and document it.
> 
> Is there any current 2.0 clock consumer that references pll-div4?
> 

I looked at T4240 for example, there's a mux node which adds pll-div4 option:
mux0: mux0 at 0 {
	#clock-cells = <0>;
	reg = <0x0 0x4>;
	compatible = "fsl,qoriq-core-mux-2.0";
	clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
		<&pll1 0>, <&pll1 1>, <&pll1 2>,
		<&pll2 0>, <&pll2 1>, <&pll2 2>;
	clock-names = "pll0", "pll0-div2", "pll0-div4",
		"pll1", "pll1-div2", "pll1-div4",
		"pll2", "pll2-div2", "pll2-div4";
	clock-output-names = "cmux0";
};

After this change <&pll0 2> will represent "pll0-div3" and not "pll0-div4".
 
> -Scott