[PATCH 2/3] dt/bindings: qoriq-clock: Add binding for the platform PLL

[Scott Wood]

On Wed, 2014-10-22 at 09:42 -0500, Emil Medve wrote:
> Signed-off-by: Emil Medve <Emilian.Medve at Freescale.com>
> Change-Id: I7950afa9650d15ec7ce2cca89bb2a1e38586d4a5
> ---
>  Documentation/devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index 5666812..407fb01 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -62,6 +62,8 @@ Required properties:
>  		It takes parent's clock-frequency as its clock.
>  	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
>  		It takes parent's clock-frequency as its clock.
> +	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
> +	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
>  - #clock-cells: From common clock binding. The number of cells in a
>  	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
>  	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
> @@ -94,7 +96,6 @@ Example for clock block and clock provider:
>  			compatible = "fsl,qoriq-sysclk-1.0";
>  			clock-output-names = "sysclk";
>  		};
> -
>  		pll0: pll0 at 800 {
>  			#clock-cells = <1>;
>  			reg = <0x800 0x4>;
> @@ -102,7 +103,6 @@ Example for clock block and clock provider:
>  			clocks = <&sysclk>;
>  			clock-output-names = "pll0", "pll0-div2";
>  		};
> -
>  		pll1: pll1 at 820 {
>  			#clock-cells = <1>;
>  			reg = <0x820 0x4>;
> @@ -110,7 +110,6 @@ Example for clock block and clock provider:
>  			clocks = <&sysclk>;
>  			clock-output-names = "pll1", "pll1-div2";
>  		};
> -
>  		mux0: mux0 at 0 {
>  			#clock-cells = <0>;
>  			reg = <0x0 0x4>;

Please don't make unrelated whitespace changes, especially when they're
changing something that's not obviously broken.

-Scott