[PATCH] clk: corenet: Update the clock bindings

[Scott Wood]

On Wed, 2014-01-22 at 20:47 -0600, Tang Yuantian-B29983 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: 2014年1月23日 星期四 8:44
> > To: Tang Yuantian-B29983
> > Cc: Wood Scott-B07421; galak at kernel.crashing.org; linuxppc-
> > dev at lists.ozlabs.org; devicetree at vger.kernel.org; Kushwaha Prabhakar-
> > B32579
> > Subject: Re: [PATCH] clk: corenet: Update the clock bindings
> > 
> > On Tue, 2014-01-21 at 10:02 +0800, Tang Yuantian wrote:
> > > From: Tang Yuantian <yuantian.tang at freescale.com>
> > >
> > > Main changs include:
> > > 	- Clarified the clock nodes' version number
> > > 	- Fixed a issue in example
> > >
> > > Singed-off-by: Tang Yuantian <Yuantian.Tang at freescale.com>
> > > ---
> > >  Documentation/devicetree/bindings/clock/corenet-clock.txt | 4 +++-
> > >  1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > > b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > > index 24711af..d6cadef 100644
> > > --- a/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > > +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> > > @@ -54,6 +54,8 @@ Required properties:
> > >  		It takes parent's clock-frequency as its clock.
> > >  	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
> > >  		It takes parent's clock-frequency as its clock.
> > > +	Note: v1.0 and v2.0 are clock version which should align to
> > > +	clockgen node's they belong to which is chassis version.
> > 
> > Instead, how about a note like this near the top of the file:
> > 
> > All references to "1.0" and "2.0" refer to the QorIQ chassis version to
> > which the chip complies.
> > 
> > Chassis Version		Example Chips
> > ---------------		-------------
> > 1.0			p4080, p5020, p5040
> > 2.0			t4240, b4860, t1040
> > 
> Better, I will update.
> 
> > 
> > BTW, this binding and the associated driver really should be called
> > "qoriq-clock", not "corenet-clock".  This would match the compatible
> > string, and it doesn't really have much to do with corenet (which is part
> > of the QorIQ chassis v1 and v2, but not *this* part).  Do you know if the
> > chassis v3 clock interface will be similar enough to share a driver?
> > 
> Doesn't QorIQ include some low-end socs, like p1022, p1020? 

Yes, but those aren't "QorIQ Chassis 1.0" or "QorIQ Chassis 2.0".
They're mpc85xx-family chips.

In any case, if "qoriq" makes sense for the compatible, I don't see why
it doesn't make sense for the driver.

> This driver has nothing to do with these boards. 
> I have no idea about chassis v3. If it has similar clock tree, this driver can be shared.
> Even the driver can't be used by v3, we can easily add v3 support since it has different
> Compatible string.

The reason I mentioned it is that chassis v3 will involve ARM chips that
have their own interconnect rather than corenet.

-Scott