[PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree

[Tang Yuantian-B29983]

Thanks for your review.

> -----Original Message-----
> From: Wood Scott-B07421
> Sent: 2013年10月29日 星期二 11:26
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; Mark Rutland; devicetree at vger.kernel.org;
> linuxppc-dev at lists.ozlabs.org; Li Yang-Leo-R58472
> Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device
> tree
> 
> On Sun, 2013-10-20 at 21:55 -0500, Tang Yuantian-B29983 wrote:
> > I didn't see how your suggestion is a better matching.
> >
> >  OSC ----> PLL1 ----> mux ----> CPU
> >       |           |
> >       |--> PLL2 --|
> >         ........
> > As your suggestion, the clock tree looks like the above.
> > In this case, the MUX driver will not know the divider details(/2, /4,
> > or /3).
> 
> When is there ever a /3?
> 
For T4, there is a /3, but it is used by PME not CPU.


> > I think the MUX should act like "switch" which choose one of the input
> > clock as a output clock. It should not CREATE clock(like PLL1/2,
> > PLL1/4).
> > The purpose of clock driver is to establish the clock tree.
> > The clock tree will not be established in your suggestion because the
> > divider is missing, we don't know where PLL/2 comes from.
> >
> > If you really like your proposal, it should be changed to this:
> >
> > OSC ------> PLL1 -----> PLL1 /1 ---------> MUX ------->CPU
> >      |            |___> PLL1 /2 _______|
> >      |                                 |
> >      |____> PLL2 -----> PLL2 /2 -------|
> >                   |___> PLL2/ 4 _______|
> >
> > (it is possible that PLLs have different divider).
> 
> Do we actually have (or expect) a situation where the PLLs have different
> dividers, or even where the same bit setting in the MUX register means a
> different divider from one chip to another (within the same MUX
> compatible string)?  If so, then I agree that we should go with your
> approach.
> 
For a specific chip, the dividers are same for each PLL.
But CPU may use ONLY one of the dividers of a PLL.
For example, on p4080, core0-3 may use PLL3/1, but do not use PLL3/2.
(I didn't deal with this situation in driver either because there are limitations to use it).

> The way Freescale documents things in chip manuals rather than in block
> manuals, with little bits of information different in each chip manual,
> makes it hard to figure out this sort of thing.  From the examples I
> looked at, it seemed pretty consistent that the low 2 bits of CLKSEL in
> the MUX were the log2 of the divider.  Are there any chips that don't
> adhere to this?
> 
Your observation is correct until then. But there is no rule on this officially.

Now I want to summary the pros and cons of your suggestion:
The pros:
1. the device tree would be simpler.

The cons:
1. cannot get the whole clock tree picture because dividers are hidden in driver.
2. no way to deal with the use case on p4080
3. need to deal with each <chip>-clockgen compatible string and pass a parameter
   to tell it what the divider is. 
4. the "log2 rule" could be incorrect in future, say, we have a divider of /5.

Any thoughts on this?

Regards,
Yuantian