[PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree

[Scott Wood]

On Thu, 2013-10-17 at 21:06 -0500, Tang Yuantian-B29983 wrote:
> > On Wed, 2013-10-16 at 21:08 -0500, Tang Yuantian-B29983 wrote:
> > > > > > That shows the dividers as being somewhere in between the PLL
> > > > > > and the
> > > > MUX.
> > > > > > The MUX is where the divider is selected.  There's nothing in
> > > > > > the PLL's programming interface that relates to the dividers.
> > > > > > As such it's simpler to model it as being part of the MUX.
> > > > > >
> > > > > > -Scott
> > > > > >
> > > > > I don't know whether it is simpler, but "modeling divider as being
> > > > > part
> > > > of the MUX"
> > > > > is your guess, right?
> > > > > If the "divider" is included in MUX, the MUX would not be called
> > "MUX".
> > > >
> > > > It's still selecting from multiple PLLs.
> > > >
> > > > > I don't know whether "divider" module exists or not. If it exists,
> > > > > it should be part of PLL or between PLL and MUX. wherever it was,
> > > > > the
> > > > device tree binding is appropriate.
> > > >
> > > > The device tree binding is unnecessarily complicated.
> > > >
> > > > > The P3041RM shows exactly each PLL has 2 outputs which definitely
> > > > > have
> > > > no "divider" at all.
> > > >
> > > > That diagram is a bit weird -- one of the outputs is used as is, and
> > > > the other is split into 1/2 and 1/4.  It doesn't really matter
> > > > though; the end result is the same.  We're describing the
> > > > programming interface, not artwork choices in the manual.
> > > >
> > > > -Scott
> > > >
> > > If the device tree needs to be modified, could you give me your
> > suggestions?
> > 
> > My suggestion is to have only one output per PLL node.  The MUX node
> > would have one input per PLL.  Dividers would be handled internally to
> > the MUX driver.
> > 
> > -Scott
> > 
> I don't think your suggestion is constructive.

Hmm?

> Your suggestion is on the premise of that the "divider" is part of MUX,
> And I think it should be part of PLL.
> MUX can't CREATE clock which PLL can. So my thought is more reasonable.
> If the device tree documents like what you said, it would have few help for driver.
> The reason is obvious that the driver is still going to deal with the "divider" 
> detail which varies from platform to platform.
> I will document as it was unless you prove your suggestion.

I can't follow this.  My point is that my suggestion better matches the
programming model, and is simpler.

-Scott