SATA hang on 8315E triggered by heavy flash write?

Xie Shaohui-B21989 B21989 at
Mon May 27 17:50:17 EST 2013

> > So it seems the NOR write break the signal Integrity of SATA.
> > I don't have schematic and board right now, could you please measure
> > signals related to NOR write to see if anything abnormal? Is the board
> > use FPGA or CPLD to control signal?
> I'll have to pass these questions on to my hardware vendor; I'm not
> equipped to do this level of hardware debugging (neither hardware nor
> knowledge!).
> > If stop NOR write, could the SATA recover and work?
> Earlier in my development, I was seeing this error and it would
> recover:
>   ata2: exception Emask 0x10 SAct 0x0 SErr 0x0 action 0xe frozen
>   ata2: PHY RDY changed
>   ata2: hard resetting link
>   ata2: Signature Update detected @ 0 msecs
>   ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 310)
>   ata2.00: configured for UDMA/133
>   ata2: EH complete
> At the current time, however, it seems that it does not recover.
> I don't know whether this is due to the speed limiting code, or if it's
> because we are doing more disk accesses (when the actual product is up
> and running).
[S.H] it seems it's not due to speed limiting code, 1.5Gbps is still used to recover link.

> I can re-do the tests with the speed limit disabled, but I won't be able
> to get to that for a few hours yet.  You can read about the speed limit
> issues in this thread:
> And my final patch (yes, a year later):
[S.H] for the speed limit issue, I checked 3.4.rc7 kernel, there seems a place can be used to limit the speed for 8315:
	if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
		temp = ioread32(csr_base + TRANSCFG);
		temp = temp & 0xffffffe0;
		iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
	} else {
		/* the speed limitation code for 8315 may can be put here.
		* just move the original code which wrapped by "#ifdef CONFIG_MPC8315_DS" here.
		* please let me know if you will give a try. */

Best Regards, 
Shaohui Xie

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